In the intensely competitive field of microelectronics, detailed analysis of a semiconductor integrated circuit product can provide valuable information as to how a particular technical problem was dealt with, overall strengths and weaknesses of a design approach, and other relevant information. This information can be used to make decisions regarding market positioning, future designs and new product development. The information resulting from the analysis of a product is typically provided through circuit extraction or reverse engineering, functional analysis and other technical means. At the core of this activity is the process of design analysis which, in this context, refers to the techniques and methodology of deriving complete or partial schematics, starting with essentially any type of integrated circuit in any process technology. For such technical information to be of strategic value it must be accurate and cost-effective, and it is very important that the information should be timely.
Most microelectronic devices are constructed using various metal layers interconnected over a bed of silicon, which contains transistors, capacitors, resistors, and other electronic components.
Currently, reverse engineering techniques employed in areas such as circuit analysis rely on manual circuit extraction. Methods of extracting circuits from existing layouts that are known in the industry, an example of which is described in U.S. Pat. Ser. No. 6,236,746 which issued to Chamberlain et al.
A circuit extraction process typically involves skilled engineers manually extracting circuit information by performing the following sequential tasks:    1. De-capping the chip containing the desired circuit.    2. Removing individual metal or polysilicon layers in order to expose each layer for imaging.    3. Capturing individual images of metal or polysilicon using film or digital camera, a SEM or an X-ray camera.    4. Creating photomosaics by physically connecting (usually taping) the images together in such a manner as to maintain image consistency.    5. Extracting circuits composed of tracing metal lines down to a base layer, identifying circuit elements, and connecting the elements in a connectivity network.    6. Organizing schematics.    7. Capturing schematics using a software tool or on paper for report production.
Due to the inherent manual intervention in the system, errors in connectivity and ‘signal line’ flow between separate images can occur. Other errors due to photographic lens topology sometimes skewing the ends of the images add to the possibility of errors in the creation of photomosaics that are exact representations of the physical circuit layout. The separate overlaying layers are traced onto a base underlying layer, such as polysilicon or metal. Upon successful completion of connectivity tracing, the circuit extraction process begins.
Once the photomosaic has been assembled, a skilled technician, familiar with the layout of semiconductor devices in silicon, examines the device and records the connection between the electronic components. The connection between circuits or ‘signal-lines’ are documented and given names to indicate location on the images as well as what circuit is connected to it. This information is then recorded as a ‘net-list’. A technician will also recognize basic building blocks such as NAND gates or inverters and create a detailed circuit diagram. This process generally creates multiple pages of schematics. The connectivity between these pages is usually kept separate, where inputs and outputs of signals are tracked. The engineer also follows naming conventions for identifying blocks, associated circuits and individual gates.
Quite often, while in the process of analyzing circuits to determine functionality, it is found that some components should not be included in the circuit pages for which they were originally characterized. When performing this analysis on a large device, these changes and amendments to the schematics become complicated and unmanageable, as well, if not recorded properly they may also add errors to the final report. Because current methods rely on manual circuit extraction, small mistakes can occur in connectivity between individual transistors, gates, or circuit blocks. Returning to the appropriate photomosaic can be difficult unless strict naming standards of blocks, associated circuits and individual gates, are kept. Due to the ever increasing complexity of modern circuits, this process can be very time consuming and is prone to human error.
Circuit extraction through electronic image recognition, as described in U.S. Pat. Ser. No. 5,086,477 which issued to Yu et al. rely on an automated method of extracting circuits by representing the image in a digitized form. The system identifies every unique cell and/or gate used in the integrated circuit. A unique abstract representation is created for each of the unique cells or gates, which are stored in a library. The system requires user intervention to determine the boundary of the underlying cell or gate. The system then attempts to associate and match all abstract features contained in the layout database to the cells in the reference library using classical template matching. However, the method is limited to gate-array or very structured standard cell integrated circuit analysis in which a large majority of the cells are identical. It is therefore inefficient for analysis of modern Application Specific Integrated Circuits (ASIC) or custom integrated circuits, which contain a large number of unique cells and/or gates. The extraction process further creates problems because the computer does not recognize the location of the extracted circuit; therefore, the net-lists are generated in a random fashion, and circuit blocks do not follow standard logic. Net-lists become complicated and unmanageable in large-scale projects.
Tools such as Cadence or Viewlogic introduce an electronic management of circuits, but successful schematic organization is still non-trivial. Often times, an engineer requires a double check of schematics against images. Knowing where each gate is vs. the appropriate photomosaic is time consuming, especially when dealing with circuits having 10,000+ logic gates as in microprocessors. The tools that are used have been adapted from circuit design tools, and are not designed for working backwards for the purposes of reverse engineering.
Other methods as those described in U.S. Pat. Ser. No. 5,999,726 which issued to Ho generate net-lists of components and reconnect these as circuit diagrams. However, these methods have similar problems in that the net-lists generated become overwhelmingly large, and traceability between schematics and their source images is not addressed.
When confronted with these issues, it becomes apparent that a tool is necessary for keeping track of circuit schematics against circuit gates on the appropriate photomosaics or SEM images. Recent advances in SEM capturing techniques have allowed for mosaic accuracy beyond optical photography. Most images are easily aligned and require very small interaction from the user; however, some interaction is still necessary. The necessity of interaction comes not only from the alignment issues but also from de-processing technologies. Although the process of removing metal layers is fairly standard, new manufacturing techniques constantly introduce new variables, and the de-processing of layers can sometimes cause problems such as over-etching and loss of data. To the user, most of these problems are easily recognizable.
Therefore, there is a need for a process and apparatus that will provide connectivity between the extracted circuits and the images from which they have been extracted. There is a further need for a method and apparatus that will allow for minor variations to be made in extracted circuit topology to correct mistakes due to process or acquisition errors.